1. Field of the Invention
The present invention relates to peripheral devices in computer systems, and more particularly to a processor with an internal register for maintaining status information for peripheral devices in a computer system.
2. Related Art
Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus. These peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller. A peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to xe2x80x9cinterruptxe2x80x9d normal processing by the central processing unit. During an interrupt, the central processing unit temporarily suspends normal processing and executes a piece of code known as an xe2x80x9cinterrupt service routinexe2x80x9d to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.
Many computer systems use a shared interrupt architecture, in which a plurality of peripheral devices can activate the same interrupt signal. One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are xe2x80x9cchainedxe2x80x9d together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit. In another commonly-used shared interrupt architecture, peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.
A shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.
However, a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically xe2x80x9cpollxe2x80x9d the peripheral devices in order to determine which peripheral devices require servicing.
This polling process can be quite time-consuming. The central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.
What is needed is a system for retrieving status information from peripheral devices in a shared interrupt architecture that reduces the amount of time and bus activity required to determine the status of the peripheral devices.
One embodiment of the present invention provides method for maintaining status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes. In order to update the status register, a peripheral device performs a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the CPU. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention can be characterized as a method for managing status information for a plurality of peripheral devices in a computer system. This method includes receiving status information from a peripheral device through a communication channel. In response to this status information, the method updates a status register coupled to a central processing unit. The method also includes receiving an interrupt from the peripheral device at the central processing unit. In response to the interrupt, the method tests the status register to determine which peripheral devices require servicing, and services any peripheral devices that require servicing.
In one embodiment of the present invention, the method includes communicating, from the peripheral device, status information through the communication channel to the status register, and sending, from the peripheral device, an interrupt to the central processing unit.
In another embodiment of the present invention, the status information is communicated to the status register by accessing a particular address in a set of reserved addresses, wherein an access to the particular address indicates a specific status for a specific peripheral device.
In another embodiment of the present invention, receiving the status information includes receiving status information through a computer system bus. In a variation on this embodiment, receiving the status information includes receiving status information from a peripheral device through a bus that also carries signals for maintaining coherency between multiple caches in the computer system. In a further variation on this embodiment, receiving the status information includes receiving status information through a processor-to-memory bus.
In another embodiment of the present invention, updating the status register to indicate the status of the peripheral device includes modifying a bit in the status register. In another embodiment, updating the status register includes updating the status register in the central processing unit. In yet another embodiment, updating the status register includes updating the status register in core logic coupled to the central processing unit.
In another embodiment of the present invention, receiving an interrupt from the peripheral device includes receiving an interrupt through a daisy-chained interrupt structure coupled between the peripheral devices and the central processing unit.
In yet another embodiment of the present invention, testing the status register to determine which peripheral devices require servicing includes executing an instruction that examines the status register and jumps to different interrupt service routines to service different peripheral devices based upon information contained in the status register.
Another embodiment of the present invention can be characterized as a method for managing status information for a plurality of peripheral devices in a computer system. This method includes receiving, at a peripheral device, status information regarding the peripheral device, and communicating the status information through a communication channel to a status register coupled to a central processing unit in the computer system. The method also includes sending, from the peripheral device, an interrupt to the central processing unit.